1. Technical Field
The present specification describes a switching power supply circuit, and more particularly, a switching power supply circuit used as a power supply circuit in electronic devices.
2. Discussion of the Background
Related-art multi-channel DC-DC converters include a plurality of DC-DC converters mounted on a single semiconductor chip. For example, a four-channel DC-DC converter includes four DC-DC converters CH1, CH2, CH3, and CH4, as illustrated in FIG. 1.
In such four-channel DC-DC converter, an initial switching phase is designed in such a manner that the timing with which each of the DC-DC converters CH1, CH2, CH3, and CH4 is turned on (i.e., is at a high level) is shifted from each other so that they do not overlap, thus preventing generation of noise and consequent malfunction of the DC-DC converter. Operation of such a DC-DC converter is described below.
FIGS. 2A and 2B together illustrate a circuit diagram of a related-art three-channel DC-DC converter 100. The three-channel DC-DC converter 100 converts an input voltage Vin input from a power supply 140 into output voltages Vo1, Vo2, and Vo3, respectively. The three-channel DC-DC converter 100 includes three step-down switching regulators 101, 102, and 103. In the switching regulator 101, a voltage-divider resistive circuit 111 divides an output voltage Vo1 into a divided voltage Vfa. An error amplification circuit 113 amplifies a difference voltage between the divided voltage Vfa and a reference voltage Vra generated from a reference voltage generation circuit 112, and outputs an amplified voltage as an error signal Sa. A triangular wave generation circuit 114 generates a triangular wave signal TWa based on a clock signal CLKa output from a clock generation circuit 104. As illustrated in FIG. 3, a phase of the triangular wave signal TWa corresponds to a frequency of the clock signal CLKa. As illustrated in FIG. 2A, a comparator circuit 115 compares a voltage of the error signal Sa output from the error amplification circuit 113 with a voltage of the triangular wave signal TWa output from the triangular wave generation circuit 114 to generate a switching pulse signal Spa for performing PWM (pulse width modulation) control, and outputs the switching pulse signal Spa to a switch circuit 116.
As illustrated in FIG. 4, when the switching pulse signal Spa is at a high level, the switch circuit 116 depicted in FIG. 2A is turned on and becomes conductive. By contrast, when the switching pulse signal Spa is at a low level, the switch circuit 116 is turned off and interrupted. As illustrated in FIG. 2A, when the switch circuit 116 is turned on, an electric current value of a coil L111 increases. By contrast, when the switch circuit 116 is turned off, a diode D111 is turned on and the electric current value of the coil L111 decreases. A smoothing capacitor C111 smoothes a ripple voltage generated when the switch circuit 116 is turned on and off, and outputs a smoothed voltage as an output voltage Vo1.
The switching regulators 102 and 103 perform operations similar to the above-described operations performed by the switching regulator 101.
As illustrated in FIGS. 2A and 2B, clock signals CLKa, CLKb, and CLKc output from the clock generation circuit 104 are input to triangular wave generation circuits 114, 124, and 134 of the switching regulators 101, 102, and 103, respectively. FIG. 5 is a timing chart illustrating a relation between the clock signals CLKa, CLKb, and CLKc input to the triangular wave generation circuits 114, 124, and 134, respectively, and switching pulse signals Spa, Spb, and Spc output under stable output voltages Vo1, Vo2, and Vo3 and constant loads 110, 120, and 130 depicted in FIGS. 2A and 2B, respectively.
As illustrated in FIG. 5, phases of the clock signals CLKa, CLKb, and CLKc are shifted from each other. FIG. 5 illustrates an example control for controlling timings for turning on switch circuits 116, 126, and 136 depicted in FIGS. 2A and 2B in synchrony with falling edges of the clock signals CLKa, CLKb, and CLKc, respectively. Alternatively, the switch circuits 116, 126, and 136 may be turned on in synchrony with rising edges of the clock signals CLKa, CLKb, and CLKc, respectively.
Further, in FIG. 5, when the switching pulse signals Spa, Spb, and Spc are at high levels, respectively, the switch circuits 116, 126, and 136 are turned on. Alternatively, the switch circuits 116, 126, and 136 may be turned on when the switching pulse signals Spa, Spb, and Spc are at low levels, respectively.
Shifting the phases of the clock signals CLKa, CLKb, and CLKc from each other to control switching phases for turning on the switch circuits 116, 126, and 136, respectively, can prevent the switch circuits 116, 126, and 136 from being turned on simultaneously, and thereby can reduce noise caused by overlapping timing for turning on the switch circuits 116, 126, and 136.
Under conditions of constant loads and stable output voltages, an arrangement like that described above is sufficient. However, fluctuation in loads and output voltages may change time periods when the switch circuits 116, 126, and 136 are turned on, and consequently timings for turning off the switch circuits 116, 126, and 136 may overlap.
FIG. 6 is a timing chart illustrating switching pulse signals Spa, Spb, Spc, and Spd output under constant loads and stable output voltages. The switching pulse signals Spa, Spb, Spc, and Spd output under constant loads are illustrated in solid lines. The switching pulse signals Spa, Spb, Spc, and Spd output for turning off under fluctuated loads or output voltages are illustrated in broken lines.
When a number of channels of the DC-DC converter 100 depicted in FIGS. 2A and 2B increases or when fluctuation in pulse signal width within which the switch circuits 116, 126, and 136 are turned off is great, timings for turning off the switch circuits 116, 126, and 136 may overlap. For example, a timing of the switching pulse signal Spb for turning off the switch circuit 126 may overlap a timing of the switching pulse signal Spd for turning off a switch circuit of an added switching regulator. Consequently, the overlapped timings may generate a large electric current and noise, resulting in a malfunction of the DC-DC converter 100.